`include "defines.v"

module mem_filter (
    
    input  wire [`RAM_DATA_WIDTH / 8 - 1: 0]    dram_w_mask_i,
    input  wire [`RAM_DATA_WIDTH - 1 : 0]       dram_w_data_i,
    input  wire                                 dram_w_en_i,
    output wire [`RAM_DATA_WIDTH - 1 : 0]       dram_r_data_o,
    input  wire [`RAM_ADDR_WIDTH - 1 : 0]       dram_addr_i,

    input  wire                                 dram_valid_i,
    output wire                                 dram_ready_o,

    output wire [`RAM_DATA_WIDTH / 8 - 1: 0]    dram_w_mask_o,
    output wire [`RAM_DATA_WIDTH - 1 : 0]       dram_w_data_o,
    output wire                                 dram_w_en_o,
    output wire [`RAM_ADDR_WIDTH - 1 : 0]       dram_addr_o,

    input  wire [`RAM_DATA_WIDTH - 1 : 0]       dram_r_data_i,
    output wire                                 dram_valid_o,
    input  wire                                 dram_ready_i,

    input  wire [`REG_BUS]                      clint_r_data_i,
    output wire                                 clint_valid_o,
    input  wire                                 clint_ready_i,

    output wire                                 skip_o
);
    wire   clint_addr_flag;
    assign clint_addr_flag = dram_addr_i[`RAM_ADDR_WIDTH - 1:16] == {{`RAM_ADDR_WIDTH - 28{1'b0}}, 12'h200};

    assign dram_r_data_o   = clint_addr_flag == 1'b0 ? dram_r_data_i : clint_r_data_i;
    assign dram_ready_o    = dram_ready_i | clint_ready_i;

    assign dram_w_mask_o   = dram_w_mask_i;
    assign dram_w_data_o   = dram_w_data_i;
    assign dram_w_en_o     = dram_w_en_i;
    assign dram_addr_o     = dram_addr_i;

    assign dram_valid_o    = clint_addr_flag == 1'b0 ? dram_valid_i : 1'b0;

    assign clint_valid_o   = clint_addr_flag == 1'b1 ? dram_valid_i : 1'b0;



    assign skip_o = dram_valid_i == 1'b1 && clint_addr_flag == 1'b1 ? 1'b1 : 1'b0;
endmodule
